(1) Field of the Invention
This invention relates to a semiconductor memory, and more particularly to a semiconductor memory that can be suitably adapted to a static random access memory, referred to hereinafter as static RAM or SRAM, which has a large capacity and operates at high speeds.
(2) Description of the Prior Art
In a static RAM in general, a signal potential difference is produced across a pair of bit lines or a pair of common data lines in order to effect data readout or data writing. For high speed readout or writing operations, it is necessary to change the logical level quickly. Thus there is known a technique of shorting a pair of bit lines or a pair of common data lines, across which the signal potential difference is produced, for equalizing the logical level for the next data. On the other hand, when the bit lines having the logical level opposite to that of the cell are connected to the memory cell at the time of row selection, the data on the memory cell may be occasionally reversed. Thus there is also known a precharging technique of transiently raising the bit line voltage towards the source voltage prior to row selection (word line selection) of the bit lines.
Such equalizing o precharging is usually performed at the time of the writing or reading and before row selection. The timing is produced by an address transition detection circuit (ATD) adapted for generating pulses by changes in the addresses. For example, according to the Japan Laid Open Patent Publication NO. 57-74884 or the U.S. Pat. No. 4355377, pulses are generated in the address transition detection circuit by the changes in the addresses so as to be transmitted to a clock generator. The signals for controlling the equalizing or precharging are output from the clock generator to actuate the equalizing or precharging circuits provided on the bit line pairs to shorten the access time.
However, during transition from the write operation to the readout operation in general, the bit lines or the common data lines are substantially in what is called fully swung state. For this reason, sufficient time is necessitated for equalizing or precharging, such that, when the speed is to be increased, it becomes difficult to terminate the equalizing or precharging operation before word line selection.
On the other hand, when pulses are produced more promptly from the address transition detection circuit, the equalizing or precharging operation can be terminated more promptly. However, as shown diagrammatically in FIG. 1, the address transition detection circuit 101 functions to collect the data at address inputs 100a to 100g, detect the address data transition and to transmit pulses to a clock generator 102. The address inputs 100a to 100g are widely distributed on a chip 103, so that it is extremely difficult to detect data transition of each address at a higher speed. The more the number of addresses, the larger is the scale of the address transition detection circuit 101 and the longer is the time involved until pulse generation.
The above mentioned problem is raised during transition from writing until readout of the SRAM data. The following problem is additionally raised when the speed is to be increased in the output circuit of the SRAM.
That is, the output signal from the output circuit (output buffer) usually has a binary logical level and the output circuit output data according to the two levels, that is, the high level of the source voltage and the low level of the ground voltage. An example of such output circuit is described in the Japan Laid Open Patent Publication NO. 62-214583 in which a precharging circuit is formed at the output terminal of the final output stage to enable high speed swinging. This precharging circuit includes each one MOS transistor between the output terminal and the source voltage and between the output terminal and the ground voltage. These MOS transistors are turned on by the equalizing signal from the address buffer to effect the precharging operation. By such precharging operation, the output level is between the two logical levels, so that high speed swinging is realized at the time of the ensuring swinging to the high or low level.
However, the output circuit having the precharging circuit suffers from the through-current flowing in the MOS transistor.
That is, during precharging, both the MOS transistor between the output terminal and the source voltage line and the MOS transistor between the output terminal and the ground voltage line are turned on to permit the through-current to flow from the source voltage line towards the ground voltage line to increase power consumption.